Real time signal analyzer

ABSTRACT

This invention relates to a real time signal analyzer that can produce time domain data and frequency domain data at the substantial same time and in real time, securing the simultaneousness between them, and can analyze them with changing the setting of the center frequency and the signal analysis span arbitrarily in low cost configuration. The apparatus has frequency conversion means  14  and  16  for shifting the frequency of input time domain data according to a selectable center frequency data and for decimating them according to a selectable decimation coefficient, a FFT processor  18  for FFT processing the output data of the frequency conversion means in real time, a delay means  28  for delaying the output data of the frequency conversion means for a predetermined time, a frequency domain data memory means  32  for storing the FFT processed frequency domain data from the FFT processor, a time domain data memory means  36  for storing the delayed time domain data read out from the delay means, and feedback means  30  and  38  for feeding the data read out from the time domain data memory means back to the frequency conversion means instead of the input time domain data.

TECHNICAL FIELD

The present invention relates to a signal analyzer that can analyze asignal in real time. More particularly, it relates to a real time signalanalyzer that can produce time domain data and frequency domain data atsubstantially the same time and in real time, securing the coincidencebetween them, and can analyze them with resetting the center frequencyand the signal analysis span arbitrarily in low cost configuration.

BACKGROUND ART

A real time FFT analyzer is a measurement apparatus that continuouslytransforms a signal under test by the process in real time without deadtime in order to extract the frequency domain component from the signalto analyze it. FIG. 2 shows a schematic block diagram of a conventionalFFT analyzer that provides such a real time process. An ADC (analog todigital converter) 10 converts a signal under test into a digital signaland then an IQ separator 12 separates it into the I (In-Phase) componentand the Q (Quadrature-Phase) component. A digital mixer 14 provides afrequency shift process to the I component data and the Q component dataaccording to a center frequency data and a decimation filter 16 providesa decimation process to these data according to a, selectable decimationcoefficient. The decimation coefficient is defined as the ratio of theelement number of the input data to that of the output data of thedecimation filter 16. The value of the decimation coefficient data isdecided depending on the setting of the data analysis span of theanalyzer. An FFT processor 18, transforms the decimated time domaindata, for example, 1024 points of the time domain data as one frame,into frequency domain data by the FFT. (Fast Fourier Transform) process.The decimation filter 16 has a data buffer (not shown) in the outputportion, for sequential storage of one frame of data, and the data arewritten in this data buffer sequentially and continuously. The FFTprocessor 18 can complete the FFT process of the previous frame duringthe storage of the new data into the data buffer that allows the realtime FFT analysis of the data. A memory 20 stores the output data of theFFT processor 18 sequentially. A trigger circuit 22 can set a triggercondition to the data in the memory 20. If the trigger condition issatisfied, the trigger circuit 22 outputs a trigger signal to read outthe data that qualify the trigger condition from the memory 20. A CPU 24controls the whole of the real time analyzer. The data read out from thememory 20 are sent to a display circuit (not shown) to display them on adisplay screen (not shown). This real time FFT analyzer can extractspectrum (or frequency component) data in real time without dead timeand can capture an event occurrence that meets an arbitrary triggercondition for record and display.

It is necessary for the described real time FFT analyzer to set a centerfrequency and a signal analysis span, but it would be difficult to setthese condition properly at the beginning if, especially, a signal undertest has a transient variation or an incidental fluctuation. In such acase, it is desirable to set a wider analysis span at first and analyzeand display the signal, and then to reset the center frequency and theanalysis span any analyze the signal again to get a magnified display ofa remarkable point of the signal component. Such a process, however, hasbeen realized in a CPU by software before so that it requires plenty oftime for the second data analysis and display process. Therefore therewas such an attempt as further provides a zoom processor 26 (FIG. 3)specialized for zoom processing in order to make the signal processfast, but this leads the system to a complicate one and then cost up.

Besides, when it conducts the signal analysis and the signal displayafter changing the center frequency and the analysis span and if thesignal is transient or incidental, it is impossible for the conventionalsignal analyzer as shown in FIGS. 2 and 3 to trace the original eventaccurately even if it acquires and analyzes the signal again.

Therefore what is desired is to provide a real time signal analyzer thatcan provide a low cost signal analysis with resetting the centerfrequency and the analysis span.

What is further desired is to provide a real time signal analyzer thatallows any times of resetting of the center frequency and the analysisspan even if the signal has a transient variation or an incidentalfluctuation.

What is further desired is to provide a real time signal analyzer thatproduces time and frequency domain data at substantially the same time,having time correspondence and securing the coincidence between them,and can analyze them with resetting the center frequency and theanalysis span.

DISCLOSURE OF INVENTION

A real time signal analyzer according to the present invention has afrequency conversion means for decimating input time domain dataaccording to a selectable decimation coefficient, an FFT processor fortransforming the output data of the frequency conversion means by theFFT process in real time, a delay means for delaying the output data ofthe frequency conversion means for a predetermined time, a frequencydomain data memory means for storing the FFT processed frequency domaindata from the FFT processor, a time domain data memory means for storingthe delayed time domain data read out from the delay means, and afeedback means for feeding the data read out from the time domain datamemory means back to the frequency conversion means instead of saidinput time domain data.

The delay means provides a predetermined delay time to the time domaindata that makes the frequency domain data in the frequency domain datamemory means and the time domain data in the time domain data memorymeans have time correspondence. It provides a repetitive FFT analysisaccording to the most suitable center frequency or decimationcoefficient by means of feeding the time domain data from the timedomain data memory means back to the frequency conversion means.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic block diagram showing a preferred exampleembodying the invention.

FIG. 2 is a schematic block diagram of an example of a conventional realtime FFT analyzer.

FIG. 3 is a schematic block diagram of an example of anotherconventional real time FFT analyzer.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 shows a schematic block diagram of a preferred example embodyingthe present invention. The same reference numbers are assigned to theseelements corresponding to those of FIGS. 2 and 3. An IQ separator 12separates input data of time domain into I and Q components. A busswitch 38 selectively provides the output data of the IQ separator 12 toa digital mixer 14. The digital mixer 14 shifts the frequency of thetime domain data according to a center frequency data. A decimationfilter 16 decimates the frequency shifted time domain data according to,a selectable decimation coefficient. The decimation coefficient, asdescribed above, is defined as the ratio of the element number of theinput data to the element number of the output data of the decimationfilter 16 for a predetermined time. For example, if the number of theinput data is 1,000 and the number of the output data is 500, thedecimation coefficient is 2. The decimation coefficient is decided bythe decimation coefficient data according to the setting of the signalanalysis span and may be 1 for non-decimation. The clock frequency ofthe output data of the decimation filter varies over a wide range, forexample, from 12.8 MHz to 128 MHz according to the variation of thedecimation coefficient. As described, the frequency shift of the digitalmixer 14 and the decimation process of the decimation filter 16 providea frequency conversion of the time domain data and produce, for example,1024 points of the time domain data as one frame in real time. Thisnumber of the data points of the one frame is just an example and wouldbe arbitrary value according to the specification of the data display orthe analysis function. An FFT processor 18 transforms the time domaindata by the FFT process and, at the same time, multiplies it by thewindow function if necessary. The time domain data of the output data ofthe decimation filter 16 is also provided to a FIFO (First In First Out)memory 28. The FIFO memory 28 is a means for delaying the time domaindata for the time corresponding to that necessary for the FFT process.

The output data of the FFT processor 18 are the frequency domain datashowing the spectrum component of the signal under test. On the otherhand, the delayed time domain data output from the FIFO 28 are delayedby a time equal to the FFT processing time of the FFT processor 18.Therefore the time domain data and the frequency domain data correspondin time and with certainty are synchronized with each other. Then it iseasy to compare them each other, for example, to compare and watch howthe time domain data and the frequency data change in accordance withthe transient variation or incidental fluctuation of the signal undertest by means of displaying their waveforms on a screen at the sametime.

The first, second and third memory banks 32, 34 and 36 store thefrequency domain data and the time domain data respectively providedfrom the FFT processor 18 and the FIFO 28 according to the setting of abus switch 30. At first, if the decimation coefficient is 1, thefrequency domain data output from the FFT processor 18 is stored in thefirst and second memory banks 32 and 34. Each of the first and secondmemory banks 32 and 34 could have a memory capacity of 1,000 frames. Onthe other hand, the time domain data output from the FIFO 28 is storedin the third memory bank 36 via the bus switch 30. The third memory bank36 could have a memory capacity of 2,000 frames. Therefore the frequencydomain data and the time domain data stored in the first, second andthird memory banks could reach to a total of 2,000 frames. These datamake it possible to display the frequency domain waveform and the timedomain waveform on a display screen (not shown) to watch them as a firstanalysis display. The display screen could be any display means such asa cathode-ray tube, a liquid crystal display and so on. Besides, aprinter or a plotter etc. may be connected to output the analyzed dataon paper media if necessary.

As described above, the frequency domain data stored in the first andsecond memory banks 32 and 34, and the time domain data stored in thethird memory bank 36 correspond in time, or are synchronized each other.Then it is easy to compare them, for example, to compare and watch howthe time domain data and the frequency domain data change in accordancewith the transient variation or the incidental fluctuation of the signalunder test by means of displaying both waveforms on the screen at thesame time. Besides, these of the frequency domain data and the timedomain data are such a data as are acquired continuously, or without“dead time”. Therefore the data certainly reflect the transientvariation and the incidental fluctuation of the signal under test.

This invention can provide a suitable magnified display according to anarbitrary setting of the center frequency and the analysis span in lowcost configuration because it recycles the time domain data stored inthe third memory bank 36. If an operator changes the setting of thecenter frequency and the analysis span of the frequency domain for amagnified display of a portion in the first analysis display it changesthe center frequency data and the decimation coefficient data accordingto the setting. The time domain data read out from the third memory bank36 are fed back to the input of the digital mixer 14 through the busswitches 30 and 38. At this time, the bus switch 38 cuts off the inputdata from the IQ separator 12. Therefore the digital mixer 14 shifts thefrequency according to the new center frequency, and the decimationfilter 16 conducts the decimation process according to the newdecimation coefficient (2 or over). Then the output data of thedecimation filter 16 is transformed by the FFT process to provide thefrequency data for the magnified display. Besides, the FIFO 28 outputsthe time domain data that have the time correspondence to the frequencydomain data for the magnified display. At this time, the bus switch 30makes the first memory bank 32 store the frequency domain data outputfrom the FFT processor 18 and the second memory bank 34 store the timedomain data output from the FIFO 28. This configuration, however,rewrites and deletes the original, or the first stored frequency domaindata in the first and second memory banks 32 and 34 so that if it isdesired to keep the original frequency domain data, another memory maybe provided to move them thereto. Anyway, since the third memory bank 36stores the original time domain data as it is, the operator watches thefrequency domain waveform displayed on the display screen (not shown),and selects another setting of the center frequency or the analysis spanto produce more suitable magnified display again.

Though this invention has been described above according to a preferredexample, it would be apparent for the skilled in the art to modify it invarious ways. For example, though the second memory bank 34 is used as ameans for selectively storing the frequency domain data or the timedomain data in the above example, different special memories may beprovided for the respective data. The first acquired frequency and timedomain data may be always kept by providing such different memories asone memory stores the first frequency and time domain data and anothermemory stores the frequency and time domain data newly acquiredaccording to a new magnified setting of the center frequency and thesignal analysis span. Each of memories may be independent or amulti-port memory may be used. As described, an engineer could choiceany physical configuration or usage of the memory for the convenience.

INDUSTRIAL APPLICABILITY

A real time signal analyzer according to the present invention that canproduce time domain data and frequency domain data at the substantialsame time and in real time, securing the simultaneousness between them.Besides, it can repetitively analyze the stored time domain data invarious settings. Therefore it can produce the most suitable analysisdata with changing the setting of the center frequency and the signalanalysis span any number of times even if the signal has a transientvariation or an incidental fluctuation. It could be realized at low costin slight modified configuration without a special processor. Itrequires no software processing and provides hardware high-speedanalysis so that it is highly useful for analysis of both of the timedomain data and the frequency domain data.

What is claimed is:
 1. A real time signal analyzer for receiving input time domain data, comprising: a frequency conversion means for shifting the frequency of time domain data according to a selectable center frequency data, and for decimating the time domain data according to a selectable decimation coefficient; an FFT processor for FFT processing the output data of the frequency conversion means in real time; a delay means for delaying the output data of the frequency conversion means for a predetermined time; a frequency domain data memory means for storing the FFT processed frequency domain data from the FFT processor; a time domain data memory means for storing the delayed time domain data read out from the delay means; and a selector means operable either for supplying the input time domain data to the frequency conversion means or for reading data out from the time domain memory means and feeding the data read out from the time domain data memory means back to the frequency conversion means.
 2. A real time signal analyzer according to claim 1, wherein the delay means sets up the delay time corresponding to the processing time of the FFT processor.
 3. A real time signal analyzer comprising: a frequency conversion means for shifting the frequency of input time domain data according to a first selectable center frequency and for decimating the input time domain data according to a first selectable decimation coefficient; an FFT processor for FFT processing the output data of the frequency conversion means in real time; a delay means for delaying the output data of the frequency conversion means for a predetermined time; a frequency domain data memory means for storing the FFT processed frequency domain data from the FFT processor; a time domain data memory means for storing the delayed time domain data read out from the delay means; and a feedback means for feeding the data read out from the time domain data memory means back to the frequency conversion means instead of the input time domain data; wherein the frequency conversion means shifts the frequency of the time domain data from the feedback means according to a second center frequency and decimates them according to a second decimation coefficient.
 4. A real time signal analyzer according to claim 3, wherein the delay means sets up the delay time corresponding to the processing time of the FFT processor.
 5. A real time signal analyzer according to claim 3, wherein the feedback means has a select means for selecting the input time domain data or the data read out from the time domain data memory means.
 6. A real time signal analyzer according to claim 1, wherein the frequency conversion means decimates the time domain data from the feedback means according to a decimation coefficient that is larger than the former one.
 7. A real time signal analyzer according to claim 3, further comprising: an analog to digital converter for converting an analog input signal to a digital signal; an IQ separator for producing the input time domain data by separating the output digital signal of the analog to digital converter into the I and Q components.
 8. A real time signal analyzer according to claim 3, wherein the frequency conversion means has a digital mixer for shifting the frequency of the input time domain data according to a selectable center frequency data, and a decimation filter for decimating the output data of the digital mixer according to a selectable decimation coefficient.
 9. A real time signal analyzer according to claim 3, wherein the time domain data memory means stores the delayed time domain data in case of the second center frequency data and the second decimation coefficient independent of those in case of the first center frequency data and the first decimation coefficient.
 10. A method of analyzing time domain data comprising: shifting the frequency of time domain data according to a selectable center frequency data, decimating the time domain data according to a selectable decimation coefficient, executing a real time FFT process on the decimated time domain data and generating frequency domain data corresponding to the decimated time domain data, storing the decimated time domain data in a time domain data memory, storing the frequency domain data in a frequency domain data memory, reading the stored time domain data and the stored frequency domain data, whereby the frequency domain data and the time domain data can be compared, and wherein the time domain data that is read from the time domain data memory corresponds to the frequency domain data. 